FIG. 1 schematically illustrates an example of a phased-lock loop (PLL) 10. The PLL 10 may be operated to produce a PLL output signal which may be a high frequency (HF) signal with an oscillation frequency Fvco and a phase that may be locked with respect to a reference signal with frequency Fref that may be a fraction of the frequency Fvco of the PLL 10. In the example, the PLL 10 comprises a frequency detector 14 (e.g., a phase frequency detector PFD), a charge pump (CPA) 16, a loop filter 17 (e.g., a low-pass filter), a voltage controlled oscillator (VCO) 18, and a frequency divider 20. The phase detector 14 may have a first input connected to an output of a reference oscillator 12, and a second input connected to an output of the frequency divider 20. The CPA 16 may have an input connected to an output of the phase detector 14. The loop filter 17 may have an input connected to the output of the CPA 16. The VCO 18 may have an input connected to an output of the loop filter 17. The frequency divider 20 may have an input connected to an output of the VCO 18.
In operation, the reference oscillator 12 may generate a reference signal which is periodic with a frequency Fref called the reference frequency. The reference signal may, for example, be a bi-level signal. Alternatively, the reference signal may be a continuous periodic signal, e.g., a square wave form. The phase detector 14 may compare the reference signal from the reference oscillator 12 against a feedback signal from the frequency divider 20. Ideally, the feedback signal is periodic and has a constant phase shift, e.g., zero, relative to the reference signal. The phase detector 14 may generate a phase detection signal that is indicative of a measure of the phase shift of the feedback signal relative to the reference signal. The CPA 16 may translate the phase detection signal into a CPA output voltage. The loop filter 17 may filter the CPA output voltage to generate a tuning voltage Vtune that may determine the oscillation frequency Fvco of the VCO 18. The VCO output signal, i.e., the oscillatory signal with frequency Fvco produced by the VCO 18, may be fed, for example, to an antenna (not shown), e.g., through a power amplifier (PA). The antenna may thus be driven to emit electromagnetic waves in accordance with the VCO output signal.
The VCO output signal may also be fed to the frequency divider 20. The frequency divider 20 may generate a frequency divider output signal which is a periodic signal, e.g., a bi-level periodic signal, which has a frequency that is a fraction Fvco/N of the oscillation frequency Fvco of the VCO 18. Thus, a negative feedback loop from the VCO 18 to the phase detector 14 may be formed. The phase detector 14 and the CPA 16 may be configured such that the tuning voltage Vtune rises when the phase shift detected by the phase detector 14 decreases and such that the tuning voltage Vtune falls when the detected phase shift increases, making the tuning voltage Vtune converge at a steady state level. The PLL 10 is said to be locked when the tuning voltage Vtune has converged.
The VCO frequency Fvco can be varied by varying the reference frequency Fref or the divider ratio N. The PLL may for example used for radio frequency or mm-wave frequency ranges The PLL 10 may, for example, be part of a radar transmitter in which the reference frequency Fref or the divider ratio N, and thus the VCO frequency Fvco, is driven to generate frequency ramps of the transmitted radar signal.
In the automotive industry for example, it is known to provide vehicles with radar systems. For example a short range radar system may be provided to aid a driver of the vehicle in determining a distance between the vehicle and nearby objects, such as other vehicles during, say, a parking manoeuvre or the like. Additionally, a longer range radar system may be provided for use with an adaptive cruise control system, whereby the cruise control system maintains a substantially constant distance between the vehicle in which the system is provided and a vehicle in front. Typically, such an automotive radar system comprises a transmitter for transmitting a carrier signal within a given frequency band, for example within a microwave frequency band of between 24 and 77 GHz, and upon which a modulation is applied. The automotive radar system further comprises a receiver for receiving a reflection of the transmitted signal reflected back by a nearby object. A delay and frequency shift between the transmitted and received signals may then be measured, and a distance between the vehicle and the nearby object by which the signal was reflected, and also a speed difference between the two, may be calculated.
FIG. 2 schematically illustrates an example of an embodiment of the charge pump16. The CPA 16 may comprise a driving stage circuit 200 and a charge pump circuit CPC 202. The driving state circuit 200 may have an input, e.g., a differential input, connected to the phase detector 14 (see FIG. 1) and be arranged to translate the phase detection signal from the phase detector 14 into a charge pump circuit driving signal for driving the charge pump circuit 202. For example, the driving state circuit 200 may be arranged to apply an amplitude scaling factor and a level shift to the received phase detection signal. In the example, the driving state circuit 200 comprises a follower or buffer circuit 196 connected in series with an adapter circuit 198. The follower circuit 196 may have an input connected to the phase detector 14. The adapter circuit 198 may have an output connected to the charge pump circuit 202. The driving state circuit 200 may further comprise a bias circuit 252 connected to one or more the follower circuit 196 and the adapter circuit 198. The bias circuit 252 may be arranged to bias one or more nodes of the driving state circuit 200 to appropriate voltage levels.
In the example, the charge pump circuit 202 comprises a low voltage provider 226 (ground potential), a high voltage provider 216, and an output 211. A supply voltage or a bias voltage may be applied between the low voltage provider 226 and the high voltage provider 216 for powering the charge pump circuit 202. To this end, the high and low voltage providers 216, 226 may be connected, for example, to a supply voltage provider (not shown) such as an AC to DC converter or a battery. The high and low voltage providers 216, 226 may be shared with the driving stage circuit 200, although this is not shown in FIG. 2.
The charge pump circuit 202 may comprise a first current source 203 and a second current source 290. They may be referred to as the charging source 203 and the discharging source 290, respectively. The charge pump circuit 202 may further comprise a first bipolar switching device 286, e.g., a first bipolar junction transistor (BJT), and a second bipolar switching device 288, e.g., a second BJT. The first and second bipolar switching devices 286, 288 may be arranged in a differential pair configuration, e.g., an emitter-coupled configuration. More specifically, the first bipolar switching device 286 may have an emitter connected to an emitter of the second bipolar switching device 288. The first and second bipolar switching devices 286, 288 may thus have a common emitter. This common emitter may be connected to the low potential provider 226 via the second current source 290. The first bipolar switching device 286 may have a collector connected to the high potential provider 216 via a first collector line. Similarly, the second bipolar switching device 288 may have a collector connected to the high potential provider 216 via a second collector line. The first collector line may comprise a resistor 292. The first collector line may comprise a low-pass filter for dampening high frequency components of the voltage. In the example, the low-pass filter is implemented by a resistor 292 and a capacitor 294, connected between a node of the first collector line and the low potential provider 226. The second collector line may comprise the first current source 203. The CPC output 211 may be provided by or connected to the collector of the second bipolar switching device 288. A base of the first bipolar switching device 286 and a base of the second bipolar switching device 288 may together provide a differential input of the CPC 202. The differential input of the CPC 202 may be connected to a differential output of the driving stage circuit 200, e.g., to a differential output of the adapter circuit 198.
The CPA 16 may operate, for example, as follows. The phase detector 14 (see FIG. 1) may provide the phase detection signal to the driving stage circuit 200. The driving stage circuit 200 may translate the phase detection signal into a differential charge pump circuit driving signal. The charge pump circuit driving signal may be applied at the differential input of the CPC 202, i.e., across the base of the first bipolar switching device 286 and the base of the second bipolar switching device 288. The second current source 290 may draw a stationary current from the common emitter of the first and second bipolar switching devices 286, 288. The first and second bipolar switching devices 286, 288 may form a switching pair which may be operated so that one of them is on while the other one is off. For instance, when the first bipolar switching device 286 is on, i.e., conductive, and the second bipolar switching device 288 is off, i.e., nonconductive, the second current source 290 may draw its current entirely from the first bipolar switching device 286. At the same time, the first current source 203 may pump charge through the CPC output 211, thus raising the voltage at the output 211, i.e., the CPC output voltage Vtune, i.e., the tuning voltage for the VCO 18. In contrast, when the first bipolar switching device 286 is off and the second bipolar switching device 288 is on, the second current source 290 may draw its current from the CPC output 211 via the second bipolar switching device 288. The current drawn by the second current source 290 may have an amplitude larger than that of the current drawn by the first current source 203 to produce a net loss of charge at the output 211. Accordingly, the voltage at the output 211 may drop.
The negative feedback mentioned above in reference to FIG. 1 may ensure that a rise of the CPC output voltage increases the time during which the second bipolar switching device 288 is on and the first bipolar switching device 286 is off. The CPC output voltage may therefore converge or settle at a stationary level. The PLL 10 is then said to be locked.
Turning to FIG. 3, the charge pump16 may comprise a driving stage circuit 200 and a charge pump circuit 202. The driving stage circuit 200 may comprise a first differential down signal input 204 and a second differential down signal input 206. The first down signal input 204 may be coupled to a first differential down signal output (not shown) of the phase and frequency detector 114 and the second down signal input 206 may be coupled to a second differential down signal output (not shown) of the phase and frequency detector 114. The first down signal input 204 may be coupled to a first resistance 208 and the second down signal input 206 may be coupled to a second resistance 210. The first resistance 208 may be coupled to a base terminal of a first NPN bipolar transistor 212 and the second resistance 210 may be coupled a base terminal of a second NPN bipolar transistor 214. A collector terminal of the first transistor 212 may be coupled to a voltage supply rail 216 via a third resistance 218 and a collector terminal of the second transistor 214 may be coupled to the voltage supply rail 216 via a fourth resistance 220. An emitter terminal of the first transistor 212 may be coupled to a collector terminal of a third NPN bipolar transistor 222 via a fifth resistance 224. An emitter terminal of the third transistor 222 may be coupled to a ground potential 226 via a sixth resistance 228. Similarly, an emitter terminal of the second transistor 214 may be coupled to a collector terminal of a fourth NPN bipolar transistor 230 via a seventh resistance 232 An emitter terminal of the fourth transistor 230 may be coupled to the ground potential 226 via an eighth resistance 234. Base terminals of the third and fourth transistors 222, 230 may be coupled together and to the ground potential 226 via a first capacitance 236. The above-described circuit configuration including: the first to eighth resistances 208, 210, 218, 220, 224, 228, 232, 234, the capacitance 236 and the first, second, third and fourth transistors 212, 214, 222, 230 constitute a buffer stage circuit.
A ground reference stage circuit of the driving stage circuit 200 may comprise a fifth NPN bipolar transistor 238 and a sixth NPN bipolar transistor 240 arranged in a differential pair configuration. A base terminal of the fifth transistor 238 may be coupled to the collector terminal of the fourth transistor 230 and a base terminal of the sixth transistor 240 may be coupled to the collector terminal of the third transistor 222. A collector terminal of the fifth transistor 238 may be coupled to a drain terminal of a first P-channel Metal Oxide Semiconductor Field Effect Transistor (MOSFET) 242; a source terminal of the first MOSFET 242 may be coupled to the supply rail 216. Similarly, a collector terminal of the sixth transistor 240 may be coupled to a drain terminal of a second P-channel MOSFET 244; a source terminal of the second MOSFET 244 may be coupled to the supply rail 216. A gate terminal of the first MOSFET 242 may be coupled to a gate terminal of the second MOSFET 244. The gate terminals of the first and second MOSFETs 242, 244 may also be coupled to the supply rail 216 via second capacitance 246. The gate terminals of the first and second MOSFETS 242, 244 may be coupled to a gate terminal of a third N-channel MOSFET 248 via a ninth resistance 250. The second and third MOSFETs may serve as a first current mirror. A source terminal of the third MOSFET 248 may be coupled to the supply rail 216 and a drain terminal of the third MOSFET 248 may be coupled to a bias circuit 252. Emitter terminals of the fifth and sixth transistors 238, 240 may be coupled to a collector terminal of a seventh NPN bipolar transistor 254. An emitter terminal of the seventh transistor 254 may be coupled to the ground potential 226 via a tenth resistance 256.
The collector terminal of the sixth transistor 240 may be coupled to first terminals of an eleventh resistance 260; a second terminal of the eleventh resistance 260 may be coupled to a collector terminal of an eighth NPN bipolar transistor 264 and to the ground potential via a third capacitance 266. A base terminal of the seventh transistor 264 may be coupled to the collector terminal thereof. An emitter terminal of the seventh transistor 264 may be coupled to the ground potential via a thirteenth resistance 268.
An amplifier circuit stage may comprise the first terminal of the eleventh resistance 260 being coupled to a base terminal of a ninth NPN bipolar transistor 270 via a fourteenth resistance 272. A first terminal of a twelfth resistance 262 may be coupled to the collector terminal of the fifth transistor 238 and a base terminal of a tenth NPN bipolar transistor 274 via a fifteenth resistance 276. A second terminal of the twelfth resistance 262 may be coupled to the collector terminal of the eighth transistor 264. Collector terminals of the ninth and tenth transistors 270, 274 may be coupled to the supply rail 216. An emitter terminal of the ninth transistor 270 may be coupled to a collector terminal of an eleventh NPN bipolar transistor 278. An emitter terminal of the eleventh transistor 278 may be coupled to the ground potential 226 via a sixteenth resistance 280. An emitter terminal of the tenth transistor 274 may be coupled to a collector terminal of a twelfth NPN bipolar transistor 282. An emitter terminal of the twelfth transistor 282 may be coupled to the ground potential 226 via a seventeenth resistance 284. Base terminals of the eleventh and twelfth transistors 278, 282 may be coupled to the base terminals of the third, fourth and seventh transistors 222, 230, 254 and the bias circuit 252.
The emitter terminals of the ninth and tenth transistors 270, 274 may be coupled to the charge pump circuit 202. In this respect, the charge pump circuit 202 may comprise a thirteenth NPN bipolar transistor 286 and a fourteenth NPN bipolar transistor 288 arranged in a differential pair configuration. A base terminal of the thirteenth transistor 286 may be coupled to the emitter terminal of the ninth transistor 270 and a base terminal of the fourteenth transistor 288 may be coupled to the emitter terminal of the tenth transistor 274; the base terminals of the thirteenth transistor 286 and the fourteenth transistor 288 may constitute differential control terminals. Emitter terminals of the thirteenth and fourteenth transistors 286, 288 may be coupled to the ground potential 226 via a pulsed current source 290; the pulsed current source may be coupled to the bias circuit 252.
A collector terminal of the thirteenth transistor 286 may be coupled to a trickle current supply rail 291 via an eighteenth resistance 292. The collector terminal of the thirteenth transistor 286 may also be coupled to the ground potential 226 via a fourth capacitance 294 and a fifth capacitance 296 coupled in series. A collector terminal of the fourteenth transistor 288 may be coupled to a drain terminal of a fourth P-channel MOSFET 201. An output 211 for coupling to the low-pass filter 104 may also be taken from the collector terminal of the fourteenth transistor 288. A source terminal of the fourth MOSFET 201 may be coupled to the trickle current supply rail 291 via a trickle current source 203; the trickle current source 203 may be coupled to the bias circuit 252. A gate terminal of the fourth MOSFET 201 may be coupled to a potential divider. In this respect, the gate terminal of the fourth MOSFET 201 may be coupled to the ground potential 226 via a nineteenth resistance 205 and to the trickle current supply rail 291 via a twentieth resistance 207.
It is pointed out that the design of the charge pump circuit 202 described in greater detail below may be independent of the details of the driving state circuit 200. Therefore, the driving stage circuit 200 may be implemented differently as compared to FIG. 3. Accordingly, the specific implementation the driving stage circuit 200 described above with reference to FIG. 3 is only an example.